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| www..com ST7162 UNIVERSAL PROGRAMMABLE DUAL PLL PRODUCT PREVIEW TWO INDEPENDENT PLL WITH 16 BITS PROGRAMMABLE DIVIDERS FROM 13 TO 65535 FOR TRANSMIT AND RECEIVE LOOPS ON CHIP REFERENCE OSCILLATOR COMMON FOR THE TWO LOOPS UP TO 16MHz WITH EXTERNAL CRYSTAL TWO INDEPENDENT PROGRAMMABLE REFERENCE COUNTERS: - 12 bits programmable counter from 13 to 4095 followed by selectable dividers by 1, 4 and 25 - 14 bits auxiliary programmable counter from 13 to 16383 A MCU CLOCK DERIVED FROM REFERENCE OSCILLATOR WITH A SELECTABLE DIVISION FACTOR OF 3 OR 4 TWO INDEPENDENT PFD (PHASE FREQUENCY DISCRIMINATOR) WITH 3 STATE OUTPUTS LOCK DETECT SIGNAL OUTPUT FOR THE TRANSMIT LOOP 3 & 4 WIRES SELECTABLE MCU SERIAL INTERFACE, FOR SIMULTANEOUS PROGRAMMING OF 2 COUNTERS STAND-BY MODE MAIN CHARACTERISTICS High input sensitivity: 200mVpkpk @ 60MHz Low consumption: 3.5mA @ 3V for the two loops Power supply voltage: 3V to 5V Operating temperature range: -25C to +70C DIP16 ORDERING NUMBER: ST7162N SO16 ORDERING NUMBER: ST7162D PIN CONNECTION (Top view) DESCRIPTION The ST7162 is a dual frequency synthesizer in High Speed CMOS technology for radio applications with a frequency up to 60MHz. The low power consumption and high flexibility make it well suitable for cordless CT0 applications in various countries. July 1993 1/17 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ST7162 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD - VSS VIN VOUT IIN, IOUT IDD, ISS Tstg Supply Voltage Input Voltage Output Voltage DC Current per pin DC Current for pin VDD or VSS Storage Temperature Parameter Value - 0.5 to +6 VSS -0.5 to VDD +0.5 VSS -0.5 to VDD +0.5 - 10 to 10 - 30 to 30 - 55 to +125 Unit V V V mA mA C 2/17 ST7162 PIN FUNCTIONS N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name CLOCK AUX DATA IN DATA IN ENABLE MCU CLOCK VSS OSC OUT OSC IN FIN RX PD RX Out RX VDD OUT TX FIN TX PD TX LD MCU Interface MCU Interface MCU Interface MCU Interface Scaled down reference frequency for clocking the MCU Negative Power Supply Oscillator Output Oscillator Input Input to the 16 bits Receive Counter Phase detector output of the Receive loop Power saving output bit for the RX loop and FIN RX divided by N1 for testing the RX input sensitivity. Positive power supply Power saving output bit for the TX loop and FIN TX divided by N2 for testing the TX input sensitivity. Input to the 16 bits Transmit counter. Phase detector output of the transmit loop Lock detect output of the transmit loop. Function ELECTRICAL CHARACTERISTICS (Tamb = 25C, voltage reference = VSS) Symbol SUPPLY VDD IDD up Supply Voltage Supply Current 200mVpkpk sinus at input; FIN RX = 36MHz, FIN TX =49MHz; loop in lock condition; fosc = 10.24MHz; no output load 200mVpkpk sinus at input; FIN RX = 36MHz; TX Loop in Power down; fosc = 10.24MHz; no output load Stand-by mode for all counters; OSCIN pin Grounded; MCU interface disabled 3V 5V 3V 5V 3V 5V 3 5.5 3.7 7.7 2.5 5.3 150 300 8 0 < VIN < VDD Input = sinus 200mVpkpk AC coupled 3V 5V 3-5V - 60 - 100 60 100 60 V mA mA mA mA A A pF A A MHz Parameter Test Condition VDD Min. Typ. Max. Unit IDDRX Supply Current IDD down Supply Current TX and RX INPUTS C IN IIN up Fmax Input Capacitance Input Current Input Frequency OSCILLATOR C IN COUT IIN up Fmax Input Capacitance Output Capacitance Input Current Input Frequency 0 < VIN < VDD DC measured 3V 5V 3-5V - 60 - 100 8 8 60 100 16 pF pF A A MHz 3/17 ST7162 ELECTRICAL CHARACTERISTICS (Tamb = 25C, voltage reference = VSS) Symbol COUT IOUT HI Parameter Output Capacitance Output Current Source VOUT = 2.7V VOUT = 4.5V Sink VOUT = 0.3V VOUT = 0.5V Three state output VPDTX, VPDRX = 0 or 5V 3V 5V 3V 5V 5V - 200 - 500 200 500 - 50 50 Test Condition VDD Min. Typ. Max. 8 Unit pF A A A A nA PHASE FREQUENCY DISCRIMINATOR IOUT LO Output Current ILEAK Leakage Current MCU INTERFACE INPUTS C IN IIN VIH Input Capacitance Input Current Input Voltage DC measured VIN = VDD or VSS High level "1" 3-5V 3V 5V VIL Input Voltage Low level "0" 3V 5V Fmax TW Input Frequency Pulse width Maximum frequency at clock input Clock and Enable inputs 3-5V 3V 5V TSU Set-up Time Data to clock Enable to clock THOLD Hold Time Clock to data 3-5V 3-5V 3V 5V TREC Recovery Time Enable to Clock 3V 5V DIGITAL OUTPUTS: OUTTX, OUTRX, MCUCLOCK, LD CLOAD VOUT IH Output Load Capacitance Output Voltage IOUT = 0, High level "1" 3V 5V VOUT LO Output Voltage IOUT = 0, Low level "0" 3V 5V IOUTHI Output Current Source VOUT = 2.7V VOUT = 4.5V Sink VOUT = 0.3V VOUT = 0.5V CLOAD = 25pF 3V 5V 3V 5V 3V 5V TLO Output Fall Time CLOAD = 25pF 3V 5V 4/17 - 200 - 500 200 500 200 100 200 100 2.95 4.95 0.05 0.05 25 pF V V V V A A A A ns ns ns ns 80 60 100 200 80 40 80 40 - 10 2.3 3.8 0.7 1.2 500 8 10 pF A V V V V KHz ns ns ns ns ns ns ns ns IOUTLO Output Current THI Output rise Time ST7162 Figure 1: Control Unit Block Diagram Sumary of Internal Registers Register A2 R0 R1 R2 R3 R4 0 0 0 0 1 Adress A1 0 0 1 1 0 A0 0 1 0 1 0 Number of Data Bits Function 13 16 16 12 14 CIRCUIT CONTROL BINARY VALUE OF N1 = RX RATIO BINARY VALUE OF N2 = TX RATIO BINARY VALUE OF N3 = REF RATIO BINARY VALUE OF N4 = AUX REF RATIO 5/17 ST7162 Description of Control Register Bit D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name TEST 1 TEST 2 TEST 3 AUXILIARY DATA SELECT REFOUT/3 TXCE RXCE RCE ARCE MUX SELECT 1 MUX SELECT 2 MUX SELECT 3 MUX SELECT 4 Used to connect internally PFD inputs REFTX and REFRX to the chosen Ref frequency output: see Table 2. Set to 0 to select 3 wires serial data bus mode at the next pattern Set to 1 to select 4 wires serial data bus mode at the next pattern Set to 0, MCUCLOCK frequency = OSC.OUT frequency / 4 Set to 1, MCUCLOCK frequency = OSC.OUT frequency / 3 TX Counter Enable bit: if set to 0, TX amplifier, counter and PFD will be in power down mode and OUTTX pin will be set to 1. RX Counter Enable bit: if set to 0, RX amplifier, counter and PFD will be in power down mode and OUTRX pin will be set to 1. Reference Counter Enable bit: if set to 0, ref counter will be in power down mode. Auxiliary Reference Counter Enable bit: if set to 0, AUX Ref counter will be in power down mode Test Mode: See Table 1. Function Table 1. TEST1 TEST2 TEST3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Status of output pin OUTTX CONTROL BIT TXCE INTERNAL POINT REFTX INTERNAL POINT FINTX/N2 INTERNAL POINT FINTX/N2 CONTROL BIT TXCE INTERNAL POINT REFTX INTERNAL POINT FINTX/N2 INTERNAL POINT FINTX/N2 Status of output pin OUTRX CONTROL BIT RXCE INTERNAL POINT REFRX INTERNAL POINT FINRX/N1 INTERNAL POINT FINRX/N1 CONTROL BIT RXCE INTERNAL POINT REFRX INTERNAL POINT FINRX/N1 INTERNAL POINT FINRX/N1 Status of TX and RX PFD NORMAL OPERATION TEST MODE NORMAL IUP TEST MODE NORMAL IDOWN TEST MODE I LEAKAGE OPERATION WITH INCREASED IUP AND IDOWN TEST MODE INCREASED IUP TEST MODE INCREASED IDOWN TEST MODE I LEAKAGE 6/17 ST7162 Figure 2: Reference Frequency Diagram. Table 2. MUX SELECT 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MUX SELECT 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MUX SELECT 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MUX SELECT 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 INPUT OF RX PFD INPUT OF TX PFD REFTX CONNECTED REFRX CONNECTED TO INTERNAL POINT TO INTERNAL POINT (see Note 2) (see Note 1) FREF FREF FREF FREF FREF/4 FREF/4 FREF/4 FREF/4 FREF/25 FREF/25 FREF/25 FREF/25 AUXFREF AUXFREF AUXFREF AUXFREF FREF FREF/4 FREF/25 AUXFREF FREF FREF/4 FREF/25 AUXFREF FREF FREF/4 FREF/25 AUXFREF FREF FREF/4 FREF/25 AUXFREF Note (1): If the 12 bits REF. counter is disabled (RCE control bit = 0) then the inputs of RX and TX PFD (REF TX and REF RX) are connected to internal point AUX REF. Note (2): If the 14 bits auxiliary reference counter is disabled (ARCE control bit = 0) then the internal point AUXFREF is replaced by FREF/ 25. 7/17 ST7162 PROGRAMMING THE REGISTER (Figs 3 to 8) When a Low level is present on the ENABLE input, information on the DATA and AUX DATA inputs are used to program the internal registers. Data are shifted at the rising edge of the clock input. First the 3 address bits of a register are sent, followed by 12 to 16 data bits, depending on the lenght of the register. The address is latched at the 3rd clock impulse following a falling edge at ENABLE input. This configuration allows to send various lenght patterns. Moreover, fixed patterns of 24 or 32 bits can be sent if dummy bits are inserted between the address bits and the first data bit. After the last data bit, a rising edge of the ENABLE input latches the information. When the VDD supply is switched on, an internal circuit proFigure 3: 3 Wires Serial Data Transmission Timing vides a reset of the control register bits. When the serial bus is not used, a Low level at clock input and a HIGH level at ENABLE inputs are applied. PROGRAMMING THE 3/4 WIRES MODE When the Auxiliary Data select bit of the control register is set to 1, the serial bus is switched in 4 wires mode at the next pattern. Then one or other of the 5 registers may be serially loaded by one or other of the DATA or AUX DATA inputs. When loading simultaneously 2 registers with different lenght, dummy bits are inserted between the address bits and the data bits of the shorter register (see fig. 8). X = DON'T CARE DATA ADDRESS D12 A2 0 A1 0 A0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 8/17 TEST 1 TEST 2 TEST 3 AUX. DATA SELECT REF OUT/3 TX COUNTER ENABLE RX COUNTER ENABLE REF. COUNTER ENABLE AUX. REF. COUNTER ENABLE MUX SELECT 1 MUX SELECT 2 MUX SELECT 3 MUX SELECT 4 ST7162 Figure 4: 3 Wires Serial Data Transmission Timing X = DON'T CARE ADDRESS A2 0 0 A1 0 1 A0 1 0 REGISTER R1 : RX COUNTER R2 : TX COUNTER DATA D15 : : : D0 MSB = 32768 LSB = 1 Figure 5: 3 Wires Serial Data Transmission Timing X = DON'T CARE ADDRESS A2 0 A1 1 A0 1 REGISTER R3 : REF. COUNTER DATA D11 : : : D0 MSB = 2048 LSB = 1 9/17 ST7162 Figure 6: 3 Wires Serial Data Transmission Timing X = DON'T CARE ADDRESS A2 1 A1 0 A0 0 REGISTER R4 : AUX REF. COUNTER DATA D13 : : : D0 MSB = 8192 LSB = 1 Figure 7: 4 Wires Serial Data Transmission Timing ADDRESS A2 AUX A2 0 0 A1 AUX A1 0 1 A0 AUX A0 1 0 REGISTER R1 : RX COUNTER R2 : TX COUNTER DATA D15, AUX D15 : : : D0, AUX D0 MSB = 32768 LSB = 1 10/17 ST7162 Figure 8: 4 Wires Serial Data Transmission Timing X = DON'T CARE ADDRESS A2 AUX A2 0 1 A1 AUX A1 1 0 A0 AUX A0 1 0 REGISTER R3 : REF COUNTER R4 : AUX REF. COUNTER D11 : : : D0 DATA MSB = 2048 AUX DATA AUX D13 : : : AUX D0 MSB = 8192 LSB = 1 LSB = 1 11/17 ST7162 PFD DESCRIPTION (pin 10 & 15) Outputs PDTX or PDRX produce an output pulse current, sourcing or sinking, whose width depends on the delay between falling edges of reference frequency and RF frequency divided. Simplified schematic of both PFD is described in figure 10. When the current output is off, PFD is in high impedance state. The voltage at PFD outputs pins depends on the loop filter and VCO characteristics (Fig. 9) Figure 9: PD Output Current vs. FIN / REF. Frequencies. REF RX (REF TX) FIN RX / N1 (FIN TX / N2) OUTPUT CURRENT TRI-STATE D93TL012 Figure 10: Simplified schematic of PFD outputs. VDD I up PDTX, PDRX OUTPUT CURRENT LOOP FILTER to VCO I down VSS When the loop is locked, to prevent a dead area in the PFD gain due to switching delays, a very Figure 11: PD output current in locked condition. T = 1/REF D93TL013 short phase offset is introduced in the loop, so the PFD output current show the following waveform Fig. 11. OUTPUT CURRENT TRI-STATE t1 = 1/OSC IN Freq. D93TL014 12/17 ST7162 Figure 12: Switching diagrams. TW CLOCK ENABLE 50% 50% THI TLO 90% OUTTX, OUTRX MCU CLOCK, LD 90% 10% D93TL015 10% ENABLE TREC 50% 50% TSU CLOCK 50% TSU FIRST CLOCK THOLD 50% LAST CLOCK DATA IN, AUX DATA IN 50% 50% D93TL016 13/17 ST7162 Figure 13: Test Circuit. 14/17 ST7162 DIP16 PACKAGE MECHANICAL DATA DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 mm TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. 15/17 ST7162 SO16 PACKAGE MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 10.1 10.0 1.27 8.89 7.6 1.27 0.75 8 (max.) 0.291 0.020 10.5 10.65 0.35 0.23 0.5 45 (typ.) 0.397 0.393 0.050 0.350 0.300 0.050 0.029 0.413 0.419 0.1 mm TYP. MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.008 0.096 0.019 0.012 16/17 ST7162 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 17/17 |
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